With increasingly scaling of features of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, it is necessary to increase doping concentrations in the channel and reduce the thickness of gate dielectric layer in order to suppress the short channel effects, prevent the source-drain punch through and increase the drive current. However, at the same time, the high carrier concentration and the strong longitudinal electrical field also cause the carrier mobility in the channel to decrease with the scaling of the features, which results in reduction of saturation drive current and a decreased cutoff frequency.
The strained channel technology is an effective way to enhance the mobility of carriers and thus can further improve the electrical performances of the devices. However, isolations among MOSFETs are generally achieved by Shallow Trench Isolations (STIs). After the STIs have been formed, the MOSFETs are formed by a series of processes such as aggressive cleaning and reactive ion etching, which causes STIs' surface reduction. As a result, the stress in the channel of the MOSFETs will decrease due to the STIs' surface reduction, and thus the performance improvement with conventional strained channel engineering is weakened.
In view of the above, there is a need for a novel semiconductor structure and a method for fabricating the same, to further enhance the channel stress and reduce the device size.